The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method of finding a minimum set of clock buffer delays for a balanced clock tree to reduce clock skew below a selected skew limit.
The present invention has application to final balancing of an initial balanced clock tree.
In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each clock buffer in a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit. In one such embodiment, a method of generating a minimum set of clock buffer delays for balancing a clock tree includes the steps of receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays such that the difference between the optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the balanced clock tree; and generating as output the minimum set of clock buffer delays.
In another embodiment, a computer program product for balancing a clock tree may be implemented by a computer to perform the following functions: receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays such that the difference between the optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the balanced clock tree; and generating as output the minimum set of clock buffer delays.